SNES Memory Mapping..Address Decoding

Super Mario World

Address Decoder 74LS139 Spec. (two independent decoders in chip) 

                            __  __ 
                       1G  |01\/16| +5V 
                       1A  |02  15| 2G 
                       1B  |03  14| 2A 
                       1Y0 |04  13| 2B 
                       1Y1 |05  12| 2Y0 
                       1Y2 |06  11| 2Y1 
                       1Y3 |07  10| 2Y2 
                       GND |08  09| 2Y3 
                            ------ 

-------------------------------------- 
|      INPUTS      |     OUTPUTS     | 
|  ENABLE | SELECT |                 | 
|    G    | A   B  | Y0  Y1  Y2  Y3  | 
-------------------------------------- 
|    H    | X   X  | H   H   H   H   | 
|    L    | L   L  | L   H   H   H   | 
|    L    | H   L  | H   L   H   H   | 
|    L    | L   H  | H   H   L   H   | 
|    L    | H   H  | H   H   H   L   | 
-------------------------------------- 
Datasheet - 74LS139







Address Decoder 74LS139 Pinout (SUPER MARIO WORLD) 
                            __  __ 
            SNES #49 /CART |01\/16| +5V 
                       A22 |02  15| (7) 
                       A21 |03  14| A20 
                   ROM /OE |04  13| RESET 
                        NC |05  12| NC 
                        NC |06  11| NC 
                      (15) |07  10| NC 
                       GND |08  09| RAM /CE 

Pins #07, #15 connected together (NC)




SNES #49 - /CART (when pulled LOW SNES comes looking for cart memory. ROM or RAM)  It is the decoders job to know when to provide the RAM and when the ROM..

Notes: (ROM /OE - High signal DISABLES output) 


Now as you see in the diagram of SMW address decoder, A22 and A21 are A and B, we will be comparing and getting results with using the table.


-------------------------------------- 
|      INPUTS      |     OUTPUTS     | 
|  ENABLE | SELECT |                 | 
|    G    | A   B  | Y0  Y1  Y2  Y3  | 
-------------------------------------- 
|    H    | X   X  | H   H   H   H   | 
|    L    | L   L  | L   H   H   H   | 
|    L    | H   L  | H   L   H   H   | 
|    L    | L   H  | H   H   L   H   | 
|    L    | H   H  | H   H   H   L   | 
-------------------------------------- 

Skip the following stuff if you just want the conclusion... You'll see it say CONCLUSION..
A22 - L
A21 - L
Low signal to pin4, ROM ENABLED. 2nd decoder disabled (High signal to 7->15).

A22 - H
A21 - L
ROM Disabled,2nd decoder disabled

A22 - L
A21 - H
ROM Disabled,2nd decoder disabled

A22 - H
A21 - H
ROM Disabled, 2nd decoder ENABLED 


WHY? You may be wondering (I certainly was..) Well now, the SRAM in SNES LoRoms gets mapped to $70:0000, and if you convert $700000 to binary you will get 


A22|A21|A20|A19|A18|A17|A16|A15|A14|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|A3|A2|A1|A0|
  1  |   1 |   1 |   0 |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  0  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |


oh look at that.. A22, A21, and A20 are set. So our address decoder here noticed that both A22 and A21 are set, so it disables ROM output and enables the 'RAM decoder,' which will make the final decisions as to whether the RAM chip becomes enabled....

2nd DECODER
-------------
Enabled when A21 and A20 are High, also disabling ROM output
Notes: The system is being Reset when RESET is Low) - so you know decoder will not enable RAM when it's L

A20 - L
RESET - L
Ram Disabled

A20 - H
RESET - L
RAM ADDRESS SET!!! but RESETTING!! so RAM Disabled

A20 - L
RESET - H
Ram Disabled..

A20 - H
RESET - H 
RAM ADDRESS SET since A22-A20 are all high!!! NOT resetting!!! WE ARE GOOD TO GO.
RAM CHIP ENABLED!!!
============================================================


Conclusion


The decoder sends SNES to ROM as long as either A22 or A21 are not set.. that's EITHER OR. if one of them is set, no ROM... (and possibly no SRAM either because), RAM is only enabled when ALL lines A22 to A20 are set... =]


So once I figured out how the address decoders worked, and how SNES used address lines (tougher for me than I make appear in this article since I now understand..) I was ready to modify the decoders for my Flash ROM.


Super Mario World is a small 512K-Byte game. It only uses 16 32-Kbyte ROM banks. thats $10 banks.. Well I'm planning on throwing in a 32Mbit flash.. So I want to get all the ROM mapped, as much as I can.. But I realize that I do want to play commercial games with my cart.. and if I go for a specialized memory map then no other games will be able to rock on my cart... anyway, here is the basic concept


Address Decoder 74LS139 MOD (SUPER MARIO WORLD)
                            __  __
            SNES #49 /CART |01\/16| +5V
                       A22 |02  15| (7)
                       A21 |03  14| A20
                /  ------- |04  13| RESET
   ROM /OE <----AND------- |05  12| NC
                \  ------- |06  11| NC
                      (15) |07  10| \---AND--> ROM /OE
                       GND |08  09| RAM /CE


Pins 4,5,6,10 all collectively go into a DUAL AND Logic Gate. if ROM /OE ever has an instance of being low, IT WILL BE SET LOW, the gate will turn all other HIGH signals to lows..

ROM /OE only appears once on the second decoder because we can only enable ROM when we are not resetting AND not using A20.. or else we use the RAM chip / do nothing (reset).

The addition of the Gate was necessary, before the addition, whenever either A22 or A21 was set, the ROM output would become disabled.. But This logic gate fix allows the ROM to continue being enabled for all Addresses using A22-A20 address bits.

This effectively enables Mapping of ROM from banks $10:0000->$7F:0000!! And of course it will be mirrored in banks $80-$FF. notice $40-$7D. The SNES maps it like

Banks  |  Addresses  | Speed | Mapping
---------+-------------+-------+---------
 $00-$3F | $0000-$1FFF | Slow  | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
         | $2000-$20FF | Fast  | Address Bus A
         | $2100-$21FF | Fast  | Address Bus B
         | $2200-$3FFF | Fast  | Address Bus A
         | $4000-$41FF | XSlow | Internal CPU registers (see Note 1 below)
         | $4200-$43FF | Fast  | Internal CPU registers (see Note 1 below)
         | $4400-$5FFF | Fast  | Address Bus A
         | $6000-$7FFF | Slow  | Address Bus A
         | $8000-$FFFF | Slow  | Address Bus A + /CART
---------+-------------+-------+---------
 $40-$7D | $0000-$FFFF | Slow  | Address Bus A + /CART
---------+-------------+-------+---------
 $7E-$7F | $0000-$FFFF | Slow  | Address Bus A + /WRAM
---------+-------------+-------+---------
 $80-$BF | $0000-$1FFF | Slow  | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
         | $2000-$20FF | Fast  | Address Bus A
         | $2100-$21FF | Fast  | Address Bus B
         | $2200-$3FFF | Fast  | Address Bus A
         | $4000-$41FF | XSlow | Internal CPU registers (see Note 1 below)
         | $4200-$43FF | Fast  | Internal CPU registers (see Note 1 below)
         | $4400-$5FFF | Fast  | Address Bus A
         | $6000-$7FFF | Slow  | Address Bus A
         | $8000-$FFFF | Note2 | Address Bus A + /CART
---------+-------------+-------+---------
 $C0-$FF | $0000-$FFFF | Note2 | Address Bus A + /CART

It maps those banks a full 64K of ROM! But since 'standard' LoROM ignores A15, the data will be repeated..
My next wonder is that if I wire my flash rom pin A15, will I be able to get ROM on $0000-$FFFF on banks $40-$7D instead of only mirrored $8000-$FFFF?